In wireless data networking, there is a trend toward data converters with higher operating speeds. One design challenge in creating higher speed data converters is to create amplifiers that can rapidly charge, discharge, and amplify signals onto large capacitors. The charging, discharging, and amplifying generally consumes a significant portion of the power in data converters that include such amplifiers.
Parasitic capacitances of the components of amplifiers tend to be a limiting factor in the speed of these amplifiers. Parasitic capacitance effectively puts a limit on the speed of amplifying voltages and getting the voltages to settle accurately. Parasitic capacitance also puts a limit on the clock rates of data converters. Nevertheless, wireless data networking standards continue to look for broadband data and require high sample rates in data converters.
Many designers tend to choose higher voltage amplifiers in order to increase Signal to Noise Ratios (SNRs), since increased SNRs can often facilitate higher speed data processing. Thus, one traditional approach for designing data converters is to simply burn more power in an amplifier by making the amplifier use a higher supply voltage. However, higher voltage transistors (e.g., thick-oxide devices), used to make higher voltage amplifiers, tend to have larger parasitic capacitance than do lower voltage transistors (e.g., thin-oxide devices). The SNR gained from increasing power usage is offset by reduced speed due to increased parasitic capacitance.
Another traditional design approach is to use folded cascode amplifiers. Folded cascode amplifiers provide greater speed and smaller parasitic capacitance than unfolded cascodes, but they also tend to use at least twice as much current. A third traditional approach is to accept the limitations and go with lower-speed data converters.